CADENCE/HSPICE/NETLIST ERROR CATALOG

Cadence error:-

1.Not able to generate netlist?

don’t worry check and save all the component starting from the basic circuit and you will be able to generate it.

2. **error**  inductor/voltage source loop found containing     0:v2 defined in subckt 0

**you have done something terrible with circuit connection check your circuit and look for the voltage source.

**if you give same input names to two different pins.

3.If you are not able to login cadence ,i mean icfb& not running?

chances are high you are not in cad/cadence folder(don’t worry these stupid mistake everybody did)

4.Should i write netlist manually or my circuit will generate it automatically?

everything i mean whatever input you have given to your circuit it will be considered by your hspice while generating netlist.

5. if you are not getting  .tro file to check your waveform ?

you might have not included .TRAN function for graph to analyze,chuck it off i did that stupid mistake.

6.Point to remember your .TRAN i mean transient period should be more than your period or else you won’t be able to analyze the circuit variations.

7. MIND it. for your job may be aborted after successful sweep then you would have given .END more than one time.

8. If you are getting generate net list error the try closing your schematic save everything and restart,you might be able to.


9.if suppose you get an error stating file missing in your hspice library,don't get frustrated
10.When I run DRC with ASSURA, an error happened as following:

reload everything the whole setup.

10.*Error* parseString: argument #1 should be either a string or a symbol (type template = "SS") - nil

It seems that I am missing a parameter, but I don't know where to define this parameter

-->I knew the reason, beacuse my .drc.Last.state file is empty.When I remove this file, ASSURA DRC works well.


11.When you are combining various part ,for example combining 8  1bit adder to make 8 bit adder,try making a common N well so that you don't get potential mismatch error.

12.nw_StampErrorConnect

Make BP layer across PMOS